6800 instruction set (6800 assembler)

Alphabet listing of instructions

ABA ADC ADD AND ASL ASR BCC BCS BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS CBA CLC CLI CLR CLV CMP COM CPX DAA DEC DES DEX EOR INC INS INX JMP JSR LDA LDS LDX LSR NEG NOP ORA PSH PUL ROL ROR RTI RTS SBA SBC SEC SEI SEV STA STS STX SUB SWI TAB TAP TBA TPA TST TSX TXS WAI

Decoding table

MSB \ LSB0123456789ABCDEF
0NOP
(INH)
TAP
(INH)
TPA
(INH)
INX
(INH)
DEX
(INH)
CLV
(INH)
SEV
(INH)
CLC
(INH)
SEC
(INH)
CLI
(INH)
SEI
(INH)
1SBA
(INH)
CBA
(INH)
TAB
(INH)
TBA
(INH)
DAA
(INH)
ABA
(ACC)
2BRA
(REL)
BHI
(REL)
BLS
(REL)
BCC
(REL)
BCS
(REL)
BNE
(REL)
BEQ
(REL)
BVC
(REL)
BVS
(REL)
BPL
(REL)
BMI
(REL)
BGE
(REL)
BLT
(REL)
BGT
(REL)
BLE
(REL)
3TSX
(INH)
INS
(INH)
PUL A
(ACC)
PUL B
(ACC)
DES
(INH)
TXS
(INH)
PSH A
(ACC)
PSH B
(ACC)
RTS
(INH)
RTI
(INH)
WAI
(INH)
SWI
(INH)
4NEG A
(ACC)
COM A
(ACC)
LSR A
(ACC)
ROR A
(ACC)
ASR A
(ACC)
ASL A
(ACC)
ROL A
(ACC)
DEC A
(ACC)
INC A
(ACC)
TST A
(ACC)
CLR A
(ACC)
5NEG B
(ACC)
COM B
(ACC)
LSR B
(ACC)
ROR B
(ACC)
ASR B
(ACC)
ASL B
(ACC)
ROL B
(ACC)
DEC B
(ACC)
INC B
(ACC)
TST B
(ACC)
CLR B
(ACC)
6NEG
(IDX)
COM
(IDX)
LSR
(IDX)
ROR
(IDX)
ASR
(IDX)
ASL
(IDX)
ROL
(IDX)
DEC
(IDX)
INC
(IDX)
TST
(IDX)
JMP
(IDX)
CLR
(IDX)
7NEG
(EXT)
COM
(EXT)
LSR
(EXT)
ROR
(EXT)
ASR
(EXT)
ASL
(EXT)
ROL
(EXT)
DEC
(EXT)
INC
(EXT)
TST
(EXT)
JMP
(EXT)
CLR
(EXT)
8SUB A
(IMM)
CMP A
(IMM)
SBC A
(IMM)
AND A
(IMM)
BIT A
(IMM)
LDA A
(IMM)
EOR A
(IMM)
ADC A
(IMM)
ORA A
(IMM)
ADD A
(IMM)
CPX A
(IMM)
BSR
(REL)
LDS
(IMM)
9SUB A
(DIR)
CMP A
(DIR)
SBC A
(DIR)
AND A
(DIR)
BIT A
(DIR)
LDA A
(DIR)
STA A
(DIR)
EOR A
(DIR)
ADC A
(DIR)
ORA A
(DIR)
ADD A
(DIR)
CPX A
(DIR)
LDS
(DIR)
STS
(DIR)
ASUB A
(IDX)
CMP A
(IDX)
SBC A
(IDX)
AND A
(IDX)
BIT A
(IDX)
LDA A
(IDX)
STA A
(IDX)
EOR A
(IDX)
ADC A
(IDX)
ORA A
(IDX)
ADD A
(IDX)
CPX A
(IDX)
JSR
(IDX)
LDS
(IDX)
STS
(IDX)
BSUB A
(EXT)
CMP A
(EXT)
SBC A
(EXT)
AND A
(EXT)
BIT A
(EXT)
LDA A
(EXT)
STA A
(EXT)
EOR A
(EXT)
ADC A
(EXT)
ORA A
(EXT)
ADD A
(EXT)
CPX A
(EXT)
JSR
(EXT)
LDS
(EXT)
STS
(EXT)
CSUB B
(IMM)
CMP B
(IMM)
SBC B
(IMM)
AND B
(IMM)
BIT B
(IMM)
LDA B
(IMM)
EOR B
(IMM)
ADC B
(IMM)
ORA B
(IMM)
ADD B
(IMM)
LDX
(IMM)
DSUB B
(DIR)
CMP B
(DIR)
SBC B
(DIR)
AND B
(DIR)
BIT B
(DIR)
LDA B
(DIR)
STA B
(DIR)
EOR B
(DIR)
ADC B
(DIR)
ORA B
(DIR)
ADD B
(DIR)
LDX
(DIR)
STX
(DIR)
ESUB B
(IDX)
CMP B
(IDX)
SBC B
(IDX)
AND B
(IDX)
BIT B
(IDX)
LDA B
(IDX)
STA B
(IDX)
EOR B
(IDX)
ADC B
(IDX)
ORA B
(IDX)
ADD B
(IDX)
LDX
(IDX)
STX
(IDX)
FSUB B
(EXT)
CMP B
(EXT)
SBC B
(EXT)
AND B
(EXT)
BIT B
(EXT)
LDA B
(EXT)
STA B
(EXT)
EOR B
(EXT)
ADC B
(EXT)
ORA B
(EXT)
ADD B
(EXT)
LDX
(EXT)
STX
(EXT)

Abbreviations:

6800 Addressing modes:

ACC - Accumulator
In accumulator addressing, either accumulator A or accumulator B is specified. These are 1- byte instructions.
Ex: ABA adds the contetns of accumulators and stores the result in accumulator A
IMM - Immediate
In immediate addressing, operand is located immediately after the opcode in the second byte of the instruction in program memory (except LDS and LDX where the operand is in the second and third bytes of the instruction). These are 2-byte or 3-byte instructions.
Ex: LDAA #$25 loads the number (25)H into accumulator A
DIR - Direct
In direct addressing, the address of the operand is contained in the second byte of the instruction. Direct addressing allows the user to directly address the lowest 256 bytes of the memory, i.e, locations 0 through 255. Enhanced execution times are achieved by storing data in these locations. These are 2-byte instructions.
Ex: LDAA $25 loads the contents of the memory address (25)H into accumulator A
EXT - Extended
In extended addressing, the address contained in the second byte of the instruction is used as the higher eight bits of the address of the operand. The third byte of the instruction is used as the lower eight bits of the address for the operand. This is an absolute address in the memory. These are 3-byte instructions.
Ex: LDAA $1000 loads the contents of the memory address (1000)H into accumulator A
IDX - Indexed
In indexed addressing, the address contained in the second byte of the instruction is added to the index register’s lowest eight bits. The carry is then added to the higher order eight bits of the index register. This result is then used to address memory. The modified address is held in a temporary address register so there is no change to the index register. These are 2-byte instructions.
Ex: LDX #$1000 or LDAA $10,X
Initially, LDX #$1000 instruction loads 1000H to the index register (X) using immediate addressing. Then LDAA $10,X instruction, using indexed addressing, loads the contents of memory address (10)H + X = 1010H into accumulator A.
INH - Implied (Inherent)
In the implied addressing mode, the instruction gives the address inherently (i.e, stack pointer, index register, etc.). Inherent instructions are used when no operands need to be fetched. These are 1 byte instructions.
Ex: INX increases the contents of the Index register by one. The address information is "inherent" in the instruction itself.
INCA increases the contents of the accumulator A by one.
DECB decreases the contents of the accumulator B by one.
REL - Relative
The relative addressing mode is used with most of the branching instructions on the 6802 microprocessor. The first byte of the instruction is the opcode. The second byte of the instruction is called the offset. The offset is interpreted as a signed 7-bit number. If the MSB (most significant bit) of the offset is 0, the number is positive, which indicates a forward branch. If the MSB of the offset is 1, the number is negative, which indicates a backward branch. This allows the user to address data in a range of -126 to +129 bytes of the present instruction. These are 2-byte instructions.
Ex:
PC    Hex Label  Instruction
0009  2004       BRA 0FH

The registers:

Statuses shown:

Symbols in the STATUSES column:

data8 8-bit immediate data

data16 16-bit immediate data

addr8 8-bit direct address

addr16 16-bit extended address

disp 8-bit signed address displacement

(HI) bits 15-8 from 16bit value

(LO) bits 7-0 from 16bit value

[...] content of ...

[[...]] implied addressing (content of [content of ...])

Logical AND

Logical OR

Logical Exclusive-OR

Data is transferred in the direction of the arrow

MNEMOSYNTAXMODEBYTESCODECYCLESCZSOAcISYMBOLIC OPERATIONDESCRIPTION
ABAABAACC1$1B2xxxxx-[A] [A] + [B]Add B to A
ADCADC A #data8IMM2$892xxxxx-[A] [A] + data8 + CAdd contents of Memory + Carry Flag to Accumulator
ADC A addr8DIR2$993[A] [A] + [addr8] + C
ADC A data8,XIDX2$A95[A] [A] + [data8 + [X]] + C
ADC A addr16EXT3$B94[A] [A] + [addr16] + C
ADC B #data8IMM2$C92[B] [B] + data8 + C
ADC B addr8DIR2$D93[B] [B] + [addr8] + C
ADC B data8,XIDX2$E95[B] [B] + [data8 + [X]] + C
ADC B addr16EXT3$F94[B] [B] + [addr16] + C
ADDADD A #data8IMM2$8B2xxxxx-[A] [A] + data8Add Memory contents to the Accumulator
ADD A addr8DIR2$9B3[A] [A] + [addr8]
ADD A data8,XIDX2$AB5[A] [A] + [data8 + [X]]
ADD A addr16EXT3$BB4[A] [A] + [addr16]
ADD B #data8IMM2$CB2[B] [B] + data8
ADD B addr8DIR2$DB3[B] [B] + [addr8]
ADD B data8,XIDX2$EB5[B] [B] + [data8 + [X]]
ADD B addr16EXT3$FB4[B] [B] + [addr16]
ANDAND A #data8IMM2$842-xx0--[A] [A] data8Memory contents AND the Accumulator to the Accumulator
AND A addr8DIR2$943[A] [A] [addr8]
AND A data8,XIDX2$A45[A] [A] [data8 + [X]]
AND A addr16EXT3$B44[A] [A] [addr16]
AND B #data8IMM2$C42[B] [B] data8
AND B addr8DIR2$D43[B] [B] [addr8]
AND B data8,XIDX2$E45[B] [B] [data8 + [X]]
AND B addr16EXT3$F44[B] [B] [addr16]
ASLASL AACC1$482xxxx--C ← 76543210 ← 0Arithmetic Shift Left. Bit 0 is set to 0.
(multiplying by two)
ASL BACC1$582
ASL data8,XIDX2$687
ASL addr16EXT3$786
ASRASR AACC1$472xxxx--76543210 → CArithmetic Shift Right. Bit 7 stays the same.
ASR BACC1$572
ASR data8,XIDX2$677
ASR addr16EXT3$776
BCCBCC dispREL2$244------(C == 0) ?
{[PC] [PC] + disp + 2}
Branch if carry clear
BCSBCS dispREL2$254------(C == 1) ?
{[PC] [PC] + disp + 2}
Branch if carry set
BEQBEQ dispREL2$274------(Z == 1) ?
{[PC] [PC] + disp + 2}
Branch if equal to zero
BGEBGE dispREL2$2C4------(S O == 0) ?
{[PC] [PC] + disp + 2}
Branch if greater than or equal to zero
BGTBGT dispREL2$2E4------(Z (S O) == 0) ?
{[PC] [PC] + disp + 2}
Branch if greater than zero
BHIBHI dispREL2$224------(C Z == 0) ?
{[PC] [PC] + disp + 2}
Branch if Accumulator contents higher than comparand
BITBIT A #data8IMM2$852-xx0--[A] data8Memory contents AND the Accumulator, but only Status register is affected.
BIT A addr8DIR2$953[A] [addr8]
BIT A data8,XIDX2$A55[A] [data8 + [X]]
BIT A addr16EXT3$B54[A] [addr16]
BIT B #data8IMM2$C52[B] data8
BIT B addr8DIR2$D53[B] [addr8]
BIT B data8,XIDX2$E55[B] [data8 + [X]]
BIT B addr16EXT3$F54[B] [addr16]
BLEBLE dispREL2$2F4------(Z (S O) == 1) ?
{[PC] [PC] + disp + 2}
Branch if less than or equal to zero
BLSBLS dispREL2$234------(C Z == 1) ?
{[PC] [PC] + disp + 2}
Branch if Accumulator contents less than or same as comparand
BLTBLT dispREL2$2D4------(S O == 1) ?
{[PC] [PC] + disp + 2}
Branch if less than zero
BMIBMI dispREL2$2B4------(S == 1) ?
{[PC] [PC] + disp + 2}
Branch if minus
BNEBNE dispREL2$264------(Z == 0) ?
{[PC] [PC] + disp + 2}
Branch if not equal to zero
BPLBPL dispREL2$2A4------(S == 0) ?
{[PC] [PC] + disp + 2}
Branch if plus
BRABRA dispREL2$204------[PC] [PC] + disp + 2Unconditional branch relative to present Program Counter contents.
BSRBSR dispREL2$8D8------[[SP]] [PC(LO)],
[[SP] - 1] [PC(HI)],
[SP] [SP] - 2,
[PC] [PC] + disp + 2
Unconditional branch to subroutine located relative to present Program Counter contents.
BVCBVC dispREL2$284------(O == 0) ?
{[PC] [PC] + disp + 2}
Branch if overflow clear
BVSBVS dispREL2$294------(O == 1) ?
{[PC] [PC] + disp + 2}
Branch if overflow set
CBACBAINH1$112xxxx--[A] - [B]Compare contents of Accumulators A and B. Only the Status register is affected.
CLCCLCINH1$0C20-----C 0Clear the Carry Flag
CLICLIINH1$0E2-----0I 0Clear the Interrupt flag to enable interrupts
CLRCLR AACC1$4F20100--[A] 0Clear the Accumulator
CLR BACC1$5F2[B] 0
CLR data8,XIDX2$6F7[data8 + [X]] 0Clear the Memory location
CLR addr16EXT3$7F6[addr16] 0
CLVCLVINH1$0A2---0--O 0Clear the Overflow flag
CMPCMP A #data8IMM2$812xxxx--[A] - data8Compare the contents of Memory and Accumulator. Only the Status register is affected.
CMP A addr8DIR2$913[A] - [addr8]
CMP A data8,XIDX2$A15[A] - [data8 + [X]]
CMP A addr16EXT3$B14[A] - [addr16]
CMP B #data8IMM2$C12[B] - data8
CMP B addr8DIR2$D13[B] - [addr8]
CMP B data8,XIDX2$E15[B] - [data8 + [X]]
CMP B addr16EXT3$F14[B] - [addr16]
COMCOM AACC1$4321xx0--[A] $FF - [A]Complement the Accumulator
COM BACC1$532[B] $FF - [B]
COM data8,XIDX2$637[data8 + [X]] $FF - [data8 + [X]]Complement the Memory Location
COM addr16EXT3$736[addr16] $FF - [addr16]
CPXCPX addr8DIR2$9C4-xxx--[X(HI)] - [addr8],
[X(LO)] - [addr8 + 1]
Compare the contents of Memory to the Index Register X
CPX data8,XIDX2$AC6[X(HI)] - [data8 + [X]],
[X(LO)] - [data8 + [X] + 1]
CPX #data16IMM3$8C3[X(HI)] - data16(HI),
[X(LO)] - data16(LO)
CPX addr16EXT3$BC5[X(HI)] - [addr16(HI)],
[X(LO)] - [addr16(LO)]
DAADAAINH1$192xxxx--Decimal Adjust Accumulator A
DECDEC AACC1$4A2-xxx--[A] [A] - 1Decrement the Accumulator
DEC BACC1$5A2[B] [B] - 1
DEC data8,XIDX2$6A7[data8 + [X]] [data8 + [X]] - 1Decrement the Memory Location
DEC addr16EXT3$7A6[addr16] [addr16] - 1
DESDESINH1$344------[SP] [SP] - 1Decrement the Stack Pointer
DEXDEXINH1$094-x----[X] [X] - 1Decrement the Index Register X
EOREOR A #data8IMM2$882-xx0--[A] [A] data8Memory contents EXLCLUSIVE OR the Accumulator
EOR A addr8DIR2$983[A] [A] [addr8]
EOR A data8,XIDX2$A85[A] [A] [data8 + [X]]
EOR A addr16EXT3$B84[A] [A] [addr16]
EOR B #data8IMM2$C82[B] [B] data8
EOR B addr8DIR2$D83[B] [B] [addr8]
EOR B data8,XIDX2$E85[B] [B] [data8 + [X]]
EOR B addr16EXT3$F84[B] [B] [addr16]
INCINC AACC1$4C2-xxx--[A] [A] + 1Increment the Accumulator
INC BACC1$5C2[B] [B] + 1
INC data8,XIDX2$6C7[data8 + [X]] [data8 + [X]] + 1Increment the Memory Location
INC addr16EXT3$7C6[addr16] [addr16] + 1
INSINSINH1$314------[SP] [SP] + 1Increment the Stack Pointer
INXINXINH1$084-x----[X] [X] + 1Increment the Index Register X
JMPJMP data8,XIDX2$6E4------[PC] data8 + [X]Jump
JMP addr16EXT3$7E3[PC] addr16
JSRJSR data8,XIDX2$AD8------[[SP]] [PC(LO)],
[[SP] - 1] [PC(HI)],
[SP] [SP] - 2,
[PC] data8 + [X]
Jump to Subroutine
JSR addr16EXT3$BD9[[SP]] [PC(LO)],
[[SP] - 1] [PC(HI)],
[SP] [SP] - 2,
[PC] addr16
LDALDA A #data8IMM2$862-xx0--[A] data8Load Accumulator from Memory
LDA A addr8DIR2$963[A] [addr8]
LDA A data8,XIDX2$A65[A] [data8 + [X]]
LDA A addr16EXT3$B64[A] [addr16]
LDA B #data8IMM2$C62[B] data8
LDA B addr8DIR2$D63[B] [addr8]
LDA B data8,XIDX2$E65[B] [data8 + [X]]
LDA B addr16EXT3$F64[B] [addr16]
LDSLDS addr8DIR2$9E4-xx0--[SP(HI)] [addr8],
[SP(LO)] [addr8 + 1]
Load the Stack Pointer
LDS data8,XIDX2$AE6[SP(HI)] [data8 + [X]],
[SP(LO)] [data8 + [X] + 1]
LDS #data16IMM3$8E3[SP(HI)] data16(HI),
[SP(LO)] data16(LO)
LDS addr16EXT3$BE5[SP(HI)] [addr16(HI)],
[SP(LO)] [addr16(LO)]
LDXLDX addr8DIR2$DE4-xx0--[X(HI)] [addr8],
[X(LO)] [addr8 + 1]
Load the Index Register
LDX data8,XIDX2$EE6[X(HI)] [data8 + [X]],
[X(LO)] [data8 + [X] + 1]
LDX #data16IMM3$CE3[X(HI)] data16(HI),
[X(LO)] data16(LO)
LDX addr16EXT3$FE5[X(HI)] [addr16(HI)],
[X(LO)] [addr16(LO)]
LSRLSR AACC1$442xx0x--0 → 76543210 → CLogical Shift Right. Bit 7 is set to 0.
(dividing by two)
LSR BACC1$542
LSR data8,XIDX2$647
LSR addr16EXT3$746
NEGNEG AACC1$402xxxx--[A] 0 - [A]Negate the Accumulator
NEG BACC1$502[B] 0 - [B]
NEG data8,XIDX2$607[data8 + [X]] 0 - [data8 + [X]]Negate the Memory Location
NEG addr16EXT3$706[addr16] 0 - [addr16]
NOPNOPINH1$012------No Operation
ORAORA A #data8IMM2$8A2-xx0--[A] [A] data8OR the Accumulator
ORA A addr8DIR2$9A3[A] [A] [addr8]
ORA A data8,XIDX2$AA5[A] [A] [data8 + [X]]
ORA A addr16EXT3$BA4[A] [A] [addr16]
ORA B #data8IMM2$CA2[B] [B] data8
ORA B addr8DIR2$DA3[B] [B] [addr8]
ORA B data8,XIDX2$EA5[B] [B] [data8 + [X]]
ORA B addr16EXT3$FA4[B] [B] [addr16]
PSHPSH AACC1$364------[[SP]] [A], [SP] [SP] - 1Push Accumulator onto the Stack
PSH BACC1$374[[SP]] [B],
[SP] [SP] - 1
PULPUL AACC1$324------[SP] [SP] + 1, [A] [[SP]]Pull Data from Stack to Accumulator
PUL BACC1$334[SP] [SP] + 1,
[B] [[SP]]
ROLROL AACC1$492xxxx--C ← 76543210 ← CRotate left through Carry.
ROL BACC1$592
ROL data8,XIDX2$697
ROL addr16EXT3$796
RORROR AACC1$462xxxx--C → 76543210 → CRotate right through Carry.
ROR BACC1$562
ROR data8,XIDX2$667
ROR addr16EXT3$766
RTIRTIINH1$3B10xxxxxx[SR] [[SP] + 1],
[B] [[SP] + 2],
[A] [[SP] + 3],
[X(HI)] [[SP] + 4],
[X(LO)] [[SP] + 5],
[PC(HI)] [[SP] + 6],
[PC(LO)] [[SP] + 7],
[SP] [SP] + 7
Return from interrupt. Put registers from Stack and increment Stack Pointer.
RTSRTSINH1$395------[PC(HI)] [[SP] + 1],
[PC(LO)] [[SP] + 2],
[SP] [SP] + 2
Return from subroutine. Pull PC from top of Stack and increment Stack Pointer.
SBASBAINH1$102xxxx--[A] [A] - [B]Subtract contents of Accumulator B from those of Accumulator A.
SBCSBC A #data8IMM2$822xxxx--[A] [A] - data8 - CSubtract Mem and Carry Flag from Accumulator
SBC A addr8DIR2$923[A] [A] - [addr8] - C
SBC A data8,XIDX2$A25[A] [A] - [data8 + [X]] - C
SBC A addr16EXT3$B24[A] [A] - [addr16] - C
SBC B #data8IMM2$C22[B] [B] - data8 - C
SBC B addr8DIR2$D23[B] [B] - [addr8] - C
SBC B data8,XIDX2$E25[B] [B] - [data8 + [X]] - C
SBC B addr16EXT3$F24[B] [B] - [addr16] - C
SECSECINH1$0D21-----C 1Set the Carry Flag
SEISEIINH1$0F2-----1I 1Set the Interrupt Flag to disable interrupts
SEVSEVINH1$0B2---1--O 1Set the Overflow Flag
STASTA A addr8DIR2$974-xx0--[addr8] [A]Store Accumulator in Memory
STA A data8,XIDX2$A76[data8 + [X]] [A]
STA A addr16EXT3$B75[addr16] [A]
STA B addr8DIR2$D74[addr8] [B]
STA B data8,XIDX2$E76[data8 + [X]] [B]
STA B addr16EXT3$F75[addr16] [B]
STSSTS addr8DIR2$9F5-xx0--[addr8] [SP(HI)],
[addr8 + 1] [SP(LO)]
Store the Stack Pointer
STS data8,XIDX2$AF7[data8 + [X]] [SP(HI)],
[data8 + [X] + 1] [SP(LO)]
STS addr16EXT3$BF6[addr16(HI)] [SP(HI)],
[addr16(LO)] [SP(LO)]
STXSTX addr8DIR2$DF5-xx0--[addr8] [X(HI)],
[addr8 + 1] [X(LO)]
Store the Index Register X
STX data8,XIDX2$EF7[data8 + [X]] [X(HI)],
[data8 + [X] + 1] [X(LO)]
STX addr16EXT3$FF6[addr16(HI)] [X(HI)],
[addr16(LO)] [X(LO)]
SUBSUB A #data8IMM2$802xxxx--[A] [A] - data8Subtract Memory contents from Accumulator
SUB A addr8DIR2$903[A] [A] - [addr8]
SUB A data8,XIDX2$A05[A] [A] - [data8 + [X]]
SUB A addr16EXT3$B04[A] [A] - [addr16]
SUB B #data8IMM2$C02[B] [B] - data8
SUB B addr8DIR2$D03[B] [B] - [addr8]
SUB B data8,XIDX2$E05[B] [B] - [data8 + [X]]
SUB B addr16EXT3$F04[B] [B] - [addr16]
SWISWIINH1$3F12-----1[[SP]] [PC(LO)],
[[SP] - 1] [PC(HI)],
[[SP] - 2] [X(LO)],
[[SP] - 3] [X(HI)],
[[SP] - 4] [A],
[[SP] - 5] [B],
[[SP] - 6] [SR],
[SP] [SP] - 7,
[PC(HI)] [$FFFA],
[PC(LO)] [$FFFB]
Software Interrupt: push registers onto Stack, decrement Stack Pointer, and jump to interrupt subroutine.
TABTABINH1$162-xx0--[B] [A]Transfer A to B
TAPTAPINH1$062xxxxx-[SR] [A]Transfer A to Status Register
TBATBAINH1$172-xx0--[A] [B]Transfer B to A
TPATPAINH1$072------[A] [SR]Transfer Status Register to A
TSTTST AACC1$4D20xx0--[A] - 0Test the Accumulator
TST BACC1$5D2[B] - 0
TST data8,XIDX2$6D7[data8 + [X]] - 0Test the Memory Location
TST addr16EXT3$7D6[addr16] - 0
TSXTSXINH1$304------[X] [SP] + 1Move Stack Pointer contents to Index register and increment.
TXSTXSINH1$354------[SP] [X] - 1Move Index register contents to Stack Pointer and decrement.
WAIWAIINH1$3E9-----1[[SP]] [PC(LO)],
[[SP] - 1] [PC(HI)],
[[SP] - 2] [X(LO)],
[[SP] - 3] [X(HI)],
[[SP] - 4] [A],
[[SP] - 5] [B],
[[SP] - 6] [SR],
[SP] [SP] - 7
Push registers onto Stack, decrement Stack Pointer, end wiat for interrupt. If [I] = 1 when WAI is executed, a non-maskable interrupt is required to exit the Wait state. Otherwise, [I] 1 when the interrupt occurs.